The present disclosure relates generally to the field of fabricating integrated circuit devices on semiconductor substrates and, more particularly, to fabricating borderless interconnections for submicron integrated circuit technologies.
An integrated circuit (IC) is formed by creating one or more devices (e.g., circuit components) on a substrate using a fabrication process. The IC's active device density (e.g., the number of devices per IC area), as well as the IC's functional density (e.g., the number of interconnected devices per IC area), are limited by the fabrication process.
An IC fabrication process generally has a number of limitations that affect the formation of a device. One of these limitations is a minimum feature size, which may be viewed as the smallest component (or line) that can be created using the process. Generally, as the feature size of the fabrication process decreases, the active device density of IC's created using the fabrication process increases because more devices may be placed on the IC. However, the devices need to be connected and, as IC technology has moved towards submicron levels, increases in functional density have become interconnection limited. This limitation presents challenges in terms of designing interconnections, identifying suitable materials for use in such interconnections, and developing processing techniques for interconnections, especially for IC generations with increasingly small feature sizes (e.g., below 0.13 μm).
An IC may include two types of vertical interconnections. Vertical interconnections that connect a metal layer and devices formed in the IC's substrate are generally referred to as “contacts.” Vertical interconnections that connect an upper metal layer with lower metal layers are generally referred to as “vias.” One difficulty in IC fabrication is making the vertical interconnections align with the features with which they are to connect. Misalignment between the vertical interconnections and the features may cause reliability issues, defects, or even failure, depending on the severity of the misalignment.
One way to increase the likelihood that a vertical interconnection is aligned with a feature is to make the feature larger than the opening of the associated contact or via. This is accomplished by creating a “border” around the contact or via opening. However, the border has an impact on the functional density of the IC, as it takes up additional space. Although some methods have been developed to eliminate the border while maintaining the needed vertical alignment, none of them are satisfactory. For example, some processes may damage one or more layers of the IC when plasma-based removal techniques are used to remove layers during fabrication. Such damage may include junction damage and contact resistance degradation in layers below the layer being removed.
Accordingly, what is needed is an improved system and method for fabricating borderless interconnections for submicron integrated circuit technologies. For example, it is desirable to fabricate borderless connections while minimizing or eliminating plasma associated damage. It is also desirable to fabricate borderless interconnections to increase the integration level and functional density of ICs.